Quantinuum Quantum Processors Excel in Error Correction Study

A recent study indicates that Quantinuum’s quantum processors demonstrate superior reliability in performing crucial operations for quantum error correction compared to other machines examined. The research also introduces a simplified method for assessing hardware readiness for these complex tasks, offering a more efficient pathway for quantum computing development.

The study, published on the arXiv preprint server, found that Quantinuum’s processors introduced substantially fewer additional errors during critical measurement and action sequences essential for error correction. Specifically, the newer Helios-1 processor excelled in tests based on a widely recognized error-correction method. Researchers needed only 50 test runs per circuit to detect performance improvements, demonstrating its efficiency. Helios-1 maintained meaningful results in larger-scale tests involving up to 91 data qubits, structured around three families of error-correction codes. These experiments evaluated the processor’s ability to execute complex operation patterns without being overwhelmed by errors. The findings, however, do not yet confirm successful error correction at these scales. This comprehensive comparison involved 10 processors from Quantinuum, IBM, and IQM, conducted by J. A. Montaez-Barrera and Kristel Michielsen from Germany’s Jlich Supercomputing Centre, with Michielsen also affiliated with the University of Cologne.

Benchmarking Quantum Error Correction Readiness

The researchers devised a specialized benchmark to gauge how effectively quantum computers execute the foundational operations for error correction. This assessment occurs before undertaking full-scale experiments with protected quantum information, saving considerable resources. A separate validation test on IBM’s Phoenix processor revealed a correlation: areas that performed better in the benchmark generally exhibited superior performance when storing an error-corrected quantum state. These results suggest the benchmark serves as an effective tool for evaluating hardware enhancements, pinpointing more reliable sections of a chip, and determining if modifications to operation scheduling improve overall performance. This offers a more accessible path to understanding quantum hardware capabilities.

The primary comparison in the study focused on the impact of intermediate measurements within a quantum computation. Such measurements are indispensable for quantum error correction, enabling a computer to detect error signs and subsequently guide corrective operations. Paradoxically, these checks can introduce new errors, disturb adjacent qubits, or cause delays for other qubits awaiting processing. To quantify this additional error burden, the researchers executed two versions of an identical task: one incorporating measurements during computation and their subsequent actions, and another without these measurement-based steps.

On the IBM processors tested, the versions involving measurements showed effective error rates roughly ten times higher than their non-measurement counterparts. In contrast, Quantinuum’s processors exhibited additional errors from measurements that were comparable in magnitude to those originating from two-qubit operations. Quantum error correction necessitates repetitive checks to preserve the integrity of quantum information. A processor must be capable of performing these checks while safeguarding the very information it aims to protect.

Quantinuum’s Helios-1 processor also demonstrated robust performance in tests based on a surface code, which protects information by organizing checks across a qubit lattice. With 25 data qubits, Helios-1 outperformed other processors at every circuit depth evaluated in this comparison. The observed differences amounted to two to four standard deviations per data point, based on 50 executions for each point. A separate comparison involving 30-qubit chains indicated a similar trend, though it was less definitive. Helios-1 recorded a lower estimated error rate, but the associated uncertainty was too substantial to draw a conclusive improvement from that measurement alone.

The larger code-based tests confirmed Helios-1’s ability to preserve useful output across various patterns of error-correction operations. For instance, experiments successfully reached 81 data qubits for surface-code structures, 91 for triangular color-code structures, and 48 for bivariate-bicycle structures–a family designed to minimize the resources needed for error correction. Each of these structures imposes distinct demands on qubit interconnections and the sequencing of measurements. In the 91-data-qubit color-code test, only seven of Helios-1’s 98 physical qubits remained available as auxiliary helpers. This constraint required researchers to divide the necessary measurements into repeated batches. Despite this challenge, the results consistently remained well above the random baseline, indicating sustained algorithmic information.

Scaling Challenges and Scheduling Optimizations

The study’s findings highlight the ongoing need for advancements, as strong performance in smaller experiments does not always translate directly to larger scales. On Helios-1, the estimated additional cost of measurements increased proportionally with the length of qubit chains tested. The study attributed this behavior to the processor’s limitations on simultaneous operations. Helios-1 features eight distinct zones where two-qubit operations and measurements can occur. A lengthy sequence involving many qubits cannot complete all its measurements concurrently, leading to some qubits remaining idle while others are being processed. These periods of waiting can significantly influence the final outcome, as detailed in the research paper.

The researchers demonstrated that modifying the operation schedule could improve performance. Initial Helios-1 experiments executed many operations sequentially. Subsequent revisions to the implementation allowed for more parallel execution of two-qubit operations and measurements, resulting in a noticeable improvement registered by the benchmark. This finding expands the test’s utility beyond processor comparisons, offering a method to determine whether different operational arrangements optimize hardware utilization. The study also documented generational improvements in smaller tests across IBM and IQM processors. IBM’s Boston generally surpassed Kingston in performance, while IQM’s Emerald showed improvements over Garnet.

However, the researchers cautioned that architectural changes can complicate direct comparisons. IBM’s transition to the square-lattice arrangement used by Phoenix altered both qubit connectivity and how circuits were mapped onto the chip. This underscores the complexity of benchmarking across diverse quantum hardware architectures.

Developing a Simplified Error-Correction Readiness Test

The reported results stem from a benchmark specifically designed to evaluate a quantum processor’s proficiency in handling the repetitive checks necessary to shield information from errors. This task, while conceptually straightforward, presents considerable practical challenges in quantum computing. Quantum error correction distributes information across multiple physical qubits to form a protected logical qubit. The quantum computer then repeatedly scans for error signatures without directly observing the protected information itself.

Auxiliary “helper” qubits perform these checks. The machine must measure these helpers, reset them for subsequent use, and, when necessary, employ the measurement outcomes to govern subsequent operations on the data qubits. Testing this entire process typically demands significant computational time and specialized software to interpret complex error signals. To address this, the researchers crafted their benchmark as a less resource-intensive, preliminary assessment.

The benchmark leverages a variant of the quantum approximate optimization algorithm (QAOA), which is designed to find good solutions to mathematical problems. The team constructed these problems in a way that required connections and measurements resembling those employed by selected error-correction codes. Adding successive layers to the calculation subjects the hardware to repeated sequences of operations. Researchers can then observe how rapidly the quality of the solutions deteriorates. For the code-based problems investigated, a score of 1 indicates optimal solutions, while 0.5 represents the outcome expected from random sampling. Results consistently above this baseline demonstrate that the circuit successfully retains useful algorithmic information.

The experiments encompassed a range of scales, from small tests with two data qubits and a single helper qubit to larger circuits involving as many as 2,950 measurements performed during computation. It is important to clarify that this benchmark does not actively correct errors in the same manner as a complete protected-memory experiment. Its primary objective is to evaluate the integrated performance of the necessary operations.

Protected Memory and Remaining Limitations

The researchers validated the practical utility of their benchmark on IBM Phoenix by comparing its results with actual error-corrected memory experiments across 11 distinct areas of the chip. Both sets of tests utilized the same physical qubits and connections within identical experimental sessions. The memory experiments assessed whether a logical qubit could retain its information through multiple rounds of error checks.

Chip areas that exhibited superior performance in the benchmark generally experienced fewer logical-memory errors. In one specific comparison, the benchmark ranked chip areas, on average, 1.6 positions away from their corresponding ranking in the memory experiment. In contrast, standard hardware calibration measures deviated by an average of 2.1 to 2.7 positions. The advantage was somewhat smaller for another stored quantum state, where a measure of the worst two-qubit gate error performed almost as effectively as the benchmark.

The memory experiments required 4,000 executions per test point, while the corresponding benchmark points needed 1,000 executions. An analysis using resampled data indicated that 500 benchmark executions could largely retain the ranking information available from 1,000 executions, suggesting a potential for even greater efficiency. This validation, however, is currently limited to small surface-code patches on a single processor. Further research is necessary to confirm whether this relationship holds true for larger codes, different hardware platforms, and significantly lower logical error rates.

The effective error rates used in the study provide a summarized view of deterioration under a simplified noise model. These rates do not represent direct measurements of every physical error occurring within a processor. Hardware constraints also influenced the feasibility of certain experiments. IQM’s conditional-control rules prevented the execution of some larger measurement-driven tests, while the connectivity limitations of IBM’s heavy-hex processors precluded direct implementation of the chosen code structures without requiring additional routing operations. The researchers suggest that more extensive testing will be needed before this type of benchmark can fully substitute for complete error-corrected experiments. Nevertheless, it offers an early and valuable insight into the critical need for quantum machines capable of repeated self-checking without compromising the very information they are designed to protect–a fundamental capability for reliable quantum computing.

For a comprehensive technical examination, readers can review the paper on arXiv. It is important to note that arXiv serves as a preprint server, facilitating rapid feedback for researchers. Neither the arXiv paper nor this article has undergone official peer review, which is a crucial step in the scientific process for verifying results.